NXP Semiconductors /MIMXRT1064 /USDHC1 /PROT_CTRL

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Interpret as PROT_CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LCTL_0)LCTL 0 (DTW_0)DTW0 (D3CD_0)D3CD 0 (EMODE_0)EMODE 0 (CDTL_0)CDTL 0 (CDSS_0)CDSS 0 (DMASEL_0)DMASEL 0 (SABGREQ_0)SABGREQ 0 (CREQ_0)CREQ 0 (RWCTL_0)RWCTL 0 (IABG_0)IABG 0 (RD_DONE_NO_8CLK)RD_DONE_NO_8CLK 0 (WECINT_0)WECINT 0 (WECINS_0)WECINS 0 (WECRM_0)WECRM 0BURST_LEN_EN 0 (NON_EXACT_BLK_RD_0)NON_EXACT_BLK_RD

NON_EXACT_BLK_RD=NON_EXACT_BLK_RD_0, WECINS=WECINS_0, SABGREQ=SABGREQ_0, CDSS=CDSS_0, IABG=IABG_0, WECINT=WECINT_0, RWCTL=RWCTL_0, DTW=DTW_0, LCTL=LCTL_0, EMODE=EMODE_0, D3CD=D3CD_0, CDTL=CDTL_0, WECRM=WECRM_0, CREQ=CREQ_0, DMASEL=DMASEL_0

Description

Protocol Control

Fields

LCTL

LED Control

0 (LCTL_0): LED off

1 (LCTL_1): LED on

DTW

Data Transfer Width

0 (DTW_0): 1-bit mode

1 (DTW_1): 4-bit mode

2 (DTW_2): 8-bit mode

D3CD

DATA3 as Card Detection Pin

0 (D3CD_0): DATA3 does not monitor Card Insertion

1 (D3CD_1): DATA3 as Card Detection Pin

EMODE

Endian Mode

0 (EMODE_0): Big Endian Mode

1 (EMODE_1): Half Word Big Endian Mode

2 (EMODE_2): Little Endian Mode

CDTL

Card Detect Test Level

0 (CDTL_0): Card Detect Test Level is 0, no card inserted

1 (CDTL_1): Card Detect Test Level is 1, card inserted

CDSS

Card Detect Signal Selection

0 (CDSS_0): Card Detection Level is selected (for normal purpose).

1 (CDSS_1): Card Detection Test Level is selected (for test purpose).

DMASEL

DMA Select

0 (DMASEL_0): No DMA or Simple DMA is selected

1 (DMASEL_1): ADMA1 is selected

2 (DMASEL_2): ADMA2 is selected

SABGREQ

Stop At Block Gap Request

0 (SABGREQ_0): Transfer

1 (SABGREQ_1): Stop

CREQ

Continue Request

0 (CREQ_0): No effect

1 (CREQ_1): Restart

RWCTL

Read Wait Control

0 (RWCTL_0): Disable Read Wait Control, and stop SD Clock at block gap when SABGREQ bit is set

1 (RWCTL_1): Enable Read Wait Control, and assert Read Wait without stopping SD Clock at block gap when SABGREQ bit is set

IABG

Interrupt At Block Gap

0 (IABG_0): Disabled

1 (IABG_1): Enabled

RD_DONE_NO_8CLK

RD_DONE_NO_8CLK

WECINT

Wakeup Event Enable On Card Interrupt

0 (WECINT_0): Disable

1 (WECINT_1): Enable

WECINS

Wakeup Event Enable On SD Card Insertion

0 (WECINS_0): Disable

1 (WECINS_1): Enable

WECRM

Wakeup Event Enable On SD Card Removal

0 (WECRM_0): Disable

1 (WECRM_1): Enable

BURST_LEN_EN

BURST length enable for INCR, INCR4 / INCR8 / INCR16, INCR4-WRAP / INCR8-WRAP / INCR16-WRAP

1 (BURST_LEN_EN_1): Burst length is enabled for INCR

NON_EXACT_BLK_RD

NON_EXACT_BLK_RD

0 (NON_EXACT_BLK_RD_0): The block read is exact block read. Host driver doesn’t need to issue abort command to terminate this multi-block read.

1 (NON_EXACT_BLK_RD_1): The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read.

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